In modern microelectronic devices that require high operating frequency and high operating speed, the rise time for the signals that are transmitted in the microelectronic circuit necessarily becomes shorter and shorter. The demand for an acceptable timing budget and noise margin also becomes more stringent. The stability of a microelectronic circuit is not only an important criterion for its application, but also directly determined by the noise immunity of the circuit. The noise immunity must cover all major sources of noises such as reflection noise, coupling noise and switching noise.
The reflection noise of a microelectronic circuit can be controlled by suitably matching the electrical resistance of the circuit, while the coupling noise can be suitably controlled by the distance between and the length of parallel lines. However, the switching noise, or sometimes known as simultaneous switching noise, which is produced by high speed turn-on/turn-off, must be filtered by utilizing high capacity decoupling capacitor or bypass capacitors. High capacity or large number of decoupling capacitors render the miniaturization of microelectronic devices impossible, i.e., it is impossible to produce thin and small devices when a large number of capacitors are required. Moreover, noise signals are proportional to the length of the current passage. The distance between the wiring that connects the capacitors to the circuit must be maintained as short as possible in order to achieve a noise filtering effect. The necessity of increasing the substrate area for positioning more capacitors and thus not achieving the desirable short distance has become a major difficulty for circuit designers.
Surface mountable devices (SMD) have been widely used in modern microelectronic circuits for their ease in fabrication. However, as surface mountable devices are miniaturized to reduce their footprints, the capacitance of the device also becomes smaller with the decreasing footprint. It is difficult to reduce the size of capacitors of high capacitance for packaging into a surface mountable device. If a large number of capacitors are used, the layout of the circuit on a substrate becomes more complicated while the packaging of the device becomes more difficult and costly.
In packaging a high pin-count (larger than 2000 pins) chip, since the capacitors for a surface mountable device is positioned at a distance from the chip, the noise signals are necessarily increased. Moreover, the longer distance between the capacitors and the chip further limits the execution speed of the device.
In order to reduce the area occupied by passive components and the fabrication cost, the current trend in microelectronic processing is to embed the passive components into the substrate. While technologies utilizing high dielectric constant materials on an organic substrate to form embedded capacitors in order to achieve high density existed, the substrate structure is complicated that it requires special fabrication steps at high cost. It also increases the difficulty in circuit layout. Moreover, the area occupied by the embedded capacitor is determined by the dielectric constant of the capacitor material, for instance, a large capacitor area is required when the dielectric constant of the capacitor material is not sufficiently high, i.e., in the case of an organic substrate such as FR-4.
It is therefore an object of the present invention to provide a buried array capacitor in microelectronic applications that does not have the drawbacks or shortcomings of the conventional imbedded capacitors.
It is another object of the present invention to provide a buried array capacitor for use in microelectronic structures that is space efficient.
It is a further object of the present invention to provide a unitary buried array capacitor formed by two layers of electrode sandwiching a middle layer of dielectric that has a dielectric constant larger than 40.
It is another further object of the present invention to provide a microelectronic structure that incorporates the present invention buried array capacitor.
It is still another object of the present invention to provide a buried array capacitor formed by unitary buried array capacitors stacked together in an up-and-down manner.
It is yet another object of the present invention to provide a buried array capacitor formed by unitary buried array capacitors positioned in a side-by-side relationship.